The present invention relates generally to the field of personal and desk top computers and more specifically to computers based upon the INTEL i486 microprocessor. The principles of the present invention however may be extended advantageously to other processors and computing environments.
The i486 employs several performance enhancing mechanisms to increase system throughput. In addition to having a full 32 bit architecture, the i486 microprocessor has an 8KByte internal cache as well as a virtual memory management unit with paging capability. The processor (i486) is also equipped to perform burst read cycles wherein a contiguous range of addresses are read from memory in a single extended bus cycle. These and other features of the i486 will be discussed briefly in the following description of applicants, preferred embodiment of their invention. The reader is referred to the i486 literature which is available from INTEL Corporation 3065 Bowers Avenue, Santa Clara, Calif. 95051. A basic understanding of the i486 processor, including the various interface signals and modes of operation, is assumed throughout.
Increased performance and code compatibility with earlier 8086, 80286, and 80386 microprocessors are reasons for the popularity of the i486 in new system designs. Unfortunately, many of the advanced features of the i486 cannot be exploited by the earlier software and thus the i486 is somewhat crippled while running the earlier code.
MS-DOS (Microsoft-Disk Operating System), a very popular operating system in the personal computer market, was written for the 8086 and 8088 microprocessors (Microsoft Corp., Redmond, Wash.) Those microprocessors did not have the memory management or multitasking capabilities of the i486. Because the virtual memory implementation in the i486 requires software to setup and manage its resources, DOS does not support and in fact is unable to use/the virtual memory management or multitasking features of the i486. Therefore, MS-DOS necessarily operates the i486 in its real (rather than protected) mode of operation in which the memory management functions are not available.
In the i486 protected mode of operation, various areas of memory may be designated as write protected in the access rights portion of the segment descriptor registers and in the page table entries used by the segmentation unit and the paging unit respectively. Both units are a part of the i486 memory manager. In the event that a program tries to write to a protected region in violation of a write protected designation, the i486 generates an exception thus allowing software to correct for the violation and reload the data if necessary. In the real mode of operation in which MS-DOS runs, these protection mechanisms are not supported. Although the internal cache may be operated transparently to software, limitations on the type of memory which may be cached are implicitly imposed when the segment and page level protections are not available.
The i486 allows write operations to alter the contents of the internal cache whether or not the data is read from a read only device such as read only memory ("ROM"). The only hardware provision for preventing such an illegal write operation is to designate all read only memory addresses as non-cacheable. If this is done, the i486 will not load the read only data into its internal cache. While this prevents the undesirable alteration of read only data, it does so at the expense of increased memory accesses. The processor and system are thus slowed down because the processor must perform memory reads every time such data is required. Aggravating the situation is the fact that accesses to read only memory, ROM, are generally slower than to the read write memory, RAM (for random access memory).
While in protected mode, the segment and page level protection mechanisms may be employed allowing the i486 to cache the read only portions of memory. Read only areas are designated as such in the appropriate attribute tables. Then if an illegal write operation occurs, an exception will be generated by the i486 and the exception handling routine can invalidate the cache entry and reload the data if necessary. While the protected mode software approach allows caching of normally non-cacheable regions of memory, it also presents a load (Central Processing Unit (CPU) time) on the processor which decreases throughput.
In the i486 real mode, the page and segment level protections are not available. The read only portions of memory, therefore, are not cacheable in real mode. Since MS-DOS operates in the real mode, the write protected regions of memory may not be cached at all if data integrity is to be ensured.
Each cache entry is called a line. The process by which the internal cache fetches data from memory is called a "line fill". A line is 16 bytes long, i.e., four Dwords (double words) (a byte is 8 bits; a word is 2 bytes or 16 bits; and a Dword is 2 words, 4 bytes, or 32 bits). The Dword is the maximum single transfer that the i486 is capable of performing by virtue of its 32 bit wide data bus. The typical i486 bus access requires a minimum of 2 clocks in a zero wait state system. During the first clock cycle the processor outputs the address and various other control signals to indicate which device is being addressed and the type of operation that is being performed. The addressed device will either send data to or receive data from the processor during the second clock cycle in a zero wait state system i.e., a system operating at maximum speed as determined by the processor clock frequency. In a i486 system, a single byte, a word, or a Dword may be transferred in this two clock bus access depending upon the instruction. If the device cannot operate at the maximum processor speed, then wait states are inserted extending the cycle to more than two clocks.
In order to speed up the line fill process, the i486 can perform burst read cycles from memory. As mentioned earlier, each line is composed of four contiguous Dwords, i.e. four adjacent 32 bit memory locations. In a burst read, the i486 reads the first Dword from memory in a two clock cycle. The address and control signals, indicating a burst read request beginning at the addressed location, are output in the first clock cycle. The first Dword is received at the processor in the second clock cycle. Then each Dword after that is received in the third, fourth, and fifth clock cycles of a burst read operation. The burst read thus differ from other read operations in that the address asserting first clock cycle is omitted in all but the first Dword transfer of the burst read cycle. The total 16 byte transfer requires only 5 clock cycles in a burst read in contrast to the 8 clocks that would be required in the ordinary i486 read.
Memory systems designed to allow burst read cycles require faster RAM than if only conventional reads were supported because data must be available in less than one clock after the address is asserted in the second, third, and fourth Dword transfers of a burst line fill.
The read performance of the i486 is greatly improved by the cache and by the burst read capability and the write performance is enhanced when there is a write hit in the cache. But the cache will not generate a line fill in response to a write miss. Thus, a very large percentage of the i486 bus accesses are memory write operations. Memory write operations to successive locations are common, particularly in the older 16 bit software. One example is where the contents of the registers are pushed onto a stack. One such instruction sequence might look like PUSH BX, PUSH CX, PUSH DX, PUSH CS, PUSH SP . . . and so on.